In recent years, reduction of a supply voltage for semiconductor integrated circuits has been pursued. In logic devices and memories mounted on portable devices and driven by batteries, in particular, lower power consumption (dissipation) is required.
In the semiconductor integrated circuit and the like, a delay circuit is employed so as to obtain signal timings required for operating respective circuits therein. On the other hand, in asynchronous, dynamic-type semiconductor memory devices that are not driven by an external clock signal, various timing signals are generated inside the semiconductor memory devices. More specifically, for various signals for controlling a memory core unit, a pulse signal is generated based on detection on a change in an address signal, a predetermined input signal, or the result of decoding of it, and a control signal in pulse form, which rises being delayed by a predetermined time and having a predetermined pulse width is generated from the pulse signal and its delayed signal.
As the background art of the present invention, an overview of an asynchronous dynamic RAM will be described below with reference to FIG. 6, which will be referred to in the embodiments of the present invention. Referring to FIG. 6, a peripheral circuit 10 controls driving of a word line driver 13 for driving a word line based on a signal indicating the result of operation by a logic circuit 12 that receives a signal supplied to a delay circuit 11 and the output of the delay circuit. A step up voltage (boost voltage) is supplied to a driving power supply of the word line driver 13 from a step-up converter (booster circuit 40). As the step-up voltage, a voltage obtained by adding a voltage exceeding a threshold voltage Vth of an NMOS transistor to a power supply voltage VDD is provided. It is noted that a reference voltage source 30 in FIG. 6 is specific to the embodiments in the present invention and is not included in the conventional dynamic RAM. In an NMOS transistor 203 of a memory cell 200 provided at an intersection between a word line and a bit line in a cell core unit 20, a high voltage not less than VDD+Vt is supplied to the gate connected to a selected word line 201 so that the output voltage of the NMOS transistor 203 can rise up to the power supply voltage VDD.
FIG. 7 is a diagram for explaining timing operations in the asynchronous dynamic RAM. When a transition in an address in memory cycle is detected by an ATD circuit not shown, an ATD signal is activated and then, a strobe signal φp for activating a row address is generated based on this signal, the result of decoding the address signal, and a control signal not shown for controlling access to the memory. By a signal generated based on this signal φp and its delayed signal, a word line rise timing and/or its pulse width are/is controlled. Likewise, a signal φSE for controlling activation of a sense amplifier 14 for amplifying a signal read onto a bit line 16 or a Y switch enable signal not shown, a control signal for precharging the bit line to ½ VDD, and the like are generated.
As the delay circuit 11 of this type, an inverter-chain constituted by connecting a plurality of inverters in cascade, for example is employed. The number of the inverters constituting the delay circuit is set to an even when the delay circuit outputs a delayed signal in phase with the input signal, and the number of the inverters is even when the delay circuit outputs a delayed signal having a phase reversed from the input signal is output.
FIG. 15 shows a configuration example of a conventional delay circuit using a CMOS inverter-chain. As shown in FIG. 15A, the conventional delay circuit is constituted from a plurality of inverters JV1 to JV4 connected in cascade, and load capacitors constituted from MOS capacitors JN1 to JN4 are connected to respective outputs of the inverters. As shown in FIG. 15B, each inverter is constituted from an PMOS transistor MP301 having its source connected to a high-potential power supply VDD, an NMOS transistor MN301 having its gate and drain connected to the gate and drain of the PMOS transistor MP301 respectively, and having its source connected to a low potential power supply GND. When a signal input to common gates undergoes a transition from a low level to a high level, electric charge on the load capacitance connected to the common drain is discharged to the power supply GND through the NMOS transistor MN301 which is in an on state, so that its output goes low. When the signal input to the common gate undergoes a transition from the high level to the low level, the load capacitance connected to the common drains is charged from the power supply VDD through the PMOS transistor MP301 which is in an on state, so that the output of the inverter goes high. As described above, by charging and discharging the load capacitances of the outputs of the inverters, signal propagation is performed.
The fall tf and rise times (delays) tf and tr of a CMOS-type inverter (which are delay times required for 10 to 90% transition of an amplitude) are derived from formulas that depend on a load capacitance, power supply voltage, transconductance, and a ratio between the power supply voltage and its threshold value, based on a drain current-voltage characteristic in the nonsaturation region and the saturation region of a MOS transistor. The characteristic between drain-to-source current and voltage in the nonsaturation region is defined by gate-to-source voltage, drain-to-source voltage, threshold voltage, and transconductance, while the characteristic between drain-to-source current and voltage in the saturation region is defined by gate-to-source voltage, threshold voltage, and transconductance. Roughly, as is well known, the rise time tf and the fall time tr are approximated by:tf=k1×CL/(βn×VDD)tr=k2×CL/(βp×VDD)where CL indicates the load capacitance, βp and βn indicate respective transconductances of the PMOS transistor and the NMOS transistor of the CMOS inverter, VDD indicates the supply voltage, and k1 and k2 are constants.
When the power supply voltage VDD is high, the rise time tr and the fall time tf of the inverter are both reduced, so that a propagation delay time tpd of the inverter decreases. The propagation delay time tpd includes a propagation delay time tpHL from rise of an input signal to fall of an inverted output signal and a propagation delay time tpLH from the fall of the input signal to the rise of the inverted output.
On the other hand, when the power supply voltage VDD is reduced, the rise time tr and the fall time tf of the inverter are both increase, so that the propagation delay time of the inverter increases.
Due to increases in delay times of the inverters JV1 to JV4 constituting the delay circuit in FIG. 15, the propagation delay time of the delay circuit also increases. Further, as in the delay circuit constituted from the inverter chain, the propagation delay time of other circuit as well decrease/increase due to elevation and lowering of an operation supply voltage. Thus, the operation speed of the device becomes fast or slow.
Recently, due to the demands in regard to a breakdown voltage with the progress in miniaturization of devices and for lower power consumption, a configuration in which the supply voltage of the semiconductor device is stepped down and internal circuits are operated at a low voltage is generally employed. In the dynamic-type semiconductor memory device as well, an internal power supply voltage VINT obtained by reducing the power supply voltage VDD supplied externally by a voltage step-down circuit is employed as the supply voltage for a peripheral circuit and a cell core section (which is also referred to as a “memory cell array”). However, the semiconductor memory device that uses the stepped-down supply voltage sometimes cannot accommodate the reduction of the power supply voltage VDD. It is because if the internal power supply voltage VINT obtained by further stepping down the reduced power supply voltage VDD is employed, the operation speed of the device becomes slow, thereby making an access time slow, so that it sometimes happens that functional specifications are not satisfied.
The conventional circuit shown in FIG. 15 also has a problem: when the power supply voltage VDD is reduced, the delay time increases more compared with an increase in the amount of the delay of an ordinary logic circuit, so that it sometimes happens that timing relationship among signals is not satisfied. This is caused by the following reason: since wiring connected to the output sections of the respective inverters is short, substantial wiring resistance is not present. Thus, the on resistance of each transistor is dominant as a resistive component which, together with the MOS capacitors, contributes to the time constant.
On contrast therewith, the signal line of the ordinary logic circuit is driven in a circuit configuration as shown in FIG. 16. Rise and fall of a signal line SL having a wiring resistance (parasitic resistance) R and a parasitic capacitance C is defined by the time constant stipulated by the parasitic resistance R of the signal line, the output resistance of a driver (output circuit) D, and the parasitic capacitance C of the signal line. In a circuit for driving a wiring having a wiring parasitic resistance as a load, the delay time of a signal is not so dependent on the power supply voltage as the inverter chain in FIG. 15.
Accordingly, the delay time of the delay circuit shown in FIG. 15 excessively increases when the supply voltage is reduced, on contrast with the ordinary logic circuit.
In order to solve the problem as described above, the inventor of the present application already proposed a delay circuit of a configuration as shown in FIG. 17 in the priority claim (US Patent Application Publication No. US 2002/0021159 A1) based on JP Patent Application No. 2001-097083. This delay circuit is the delay circuit of which the delay time does not excessively increase, compared with the ordinary logic circuit even if the supply voltage is reduced and can suppress the increase of the delay time.
Referring to FIG. 17, the delay circuit includes a plurality of inverters V11, V12, V13, and V14 connected in cascade. PMOS capacitors P11 and P12 are provided between the output of the inverter V11 and the high potential power supply VDD and the output of the inverter V13 and the high potential power supply VDD, respectively. NMOS capacitors N11 and N12 are provided between the output of the inverter V12 and the low potential power supply GND and the output of the inverter V14 and the low potential power supply GND, respectively.
The PMOS capacitors P11 and P12 become from an off state to the on state (inversion state) in response to falling transition of the outputs of the inverters V11 and V13 from the high level to the low level, respectively. The NMOS capacitors N11 and N12 become from the off state to the on state (inversion state) in response to rising transition of the outputs of the inverters V12 and V14 from the low level to the high level, respectively. As is well known, the NMOS capacitor is in an accumulation state when its gate voltage Vg is negative or a ground voltage GND (0V), and its capacitance value is constituted from a capacitance Co of a gate oxide film therein alone. When the gate voltage Vg is larger than 0, a depletion layer is formed in the surface of a substrate, so that its capacitance value becomes a capacitance C obtained by series synthesis of the gate oxide film capacitance Co and a capacitance Cd of the depletion layer formed in the surface of the substrate, which is smaller than Co. When the gate voltage Vg is positive and increases (Vg>Vt, in which Vt is the threshold voltage), an inversion layer resulting from polarity inversion of the surface of the p-type substrate is formed. If so-called strong inversion occurs, its capacitance value becomes closer to Co. Likewise, the PMOS capacitor is in the accumulation state when its gate voltage is the power supply voltage VDD. Then, when the gate voltage falls below the supply voltage and transitions toward the ground voltage GND, the PMOS capacitor becomes a depletion state and then an inversion state.
In the inverter chain shown in FIG. 17, assume that the power supply voltage VDD is reduced, the driving currents of the MOS transistors are reduced and then the on resistances of the MOS transistors constituting the inverters increase in appearance. Then, the capacitance values of the MOS capacitors relatively decrease. An increase in the amount of the delay is thereby suppressed. This delay circuit suppresses an excessive increase in the delay time due to lowering of the power supply voltage VDD, in response to rise (transition from GND to VDD) of an input SIN to the inverter V11 in the first stage.
The inventor of this application already proposed a delay circuit of a configuration as shown in FIG. 18 in JP Patent Application No. 2001-097083. This delay circuit is the delay circuit of which the delay time does not excessively increase and which can suppress an increase in the delay circuit, even if the supply voltage is reduced. Referring to FIG. 18, the threshold value of a PMOS transistor P81 of an inverter V81 is set to be high, and the threshold value of an NMOS transistor N81 of the inverter V81 is set to be low. The threshold value of a PMOS transistor P82 of an inverter V82 is set to be low and the threshold value of an NMOS transistor N82 of the inverter V82 is set to be high. The input threshold value of the inverter V81 tends to decrease as the power supply voltage is reduced, while the input threshold value of the inverter V82 tends to rise as the power supply voltage is reduced. The input threshold value of the delay circuit thereby decreases in a region in which the power supply voltage VDD is low, and the propagation delay time tpd from the rise of the input signal to the rise of the output signal becomes relatively shorter than the propagation delay time from the fall of the input signal to the fall of the output signal. As a result, the delay time in the rise of the signal can be reduced, so that dependency of this delay time on the power supply voltage is suppressed.
As described above, the delay circuits shown in FIGS. 17 and 18, respectively, suppress an excessive increase in the delay time caused by reduction of the power supply voltage VDD in the configuration as shown in FIG. 15. However, the delay circuits do not have a reverse sensitivity characteristic in which the delay time thereof decreases with reduction of the power supply voltage. For this reason, with respect to reduction of the power supply voltage of the semiconductor memory device, when edges and pulses of a control signal are generated for using the delay circuits shown in FIGS. 17 and 18, respectively, the delay of the control signal does not decrease as the power supply voltage is reduced. Thus, a constraint is imposed on the lower power consumption.
Accordingly, it is an object of the present invention to provide a semiconductor memory device in which by speeding up access to the cell core unit while reducing a power supply voltage for driving, reduction of a combined access speed to the cell core unit and the peripheral circuit caused by the reduced power supply voltage is suppressed, and its control method.
Still other object of the present invention is to provide a semiconductor device in which due to its simple configuration, an increase in the delay time caused by the reduction of the power supply voltage is further suppressed, so that the delay time shows a tendency of decreasing.